1. Field of the Invention
This present invention relates generally to the field of integrated circuit design and, more specifically, to a memory device design that facilitates detection of short circuits between bitlines in a memory device.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Memory devices, such as static random access memory (“SRAM”) and dynamic random access memory (“DRAM”), may include arrays of memory cells that each store a bit or element of data. Each data bit or element may represent a logical low (“0”) or a logical high (“1”), which may correspond to a voltage level of a circuit element disposed within the memory cell. As an example, a voltage level close to ground may be representative a logical low or “0” and a voltage level close to a supply voltage for the memory device may be representative of a logical high or “1.” The electrical paths that carry the voltage representing a bit or element of data to and from memory cells may be referred to as a data line, a bitline or a digit line. A DRAM device may additionally include wordlines, which enable a plurality of bitlines to be accessed so that data may be written to or read from corresponding memory cells.
Some memory devices have complementary bitlines for each memory cell. The complementary bitlines are designed so that they are always in opposite logic states. In other words, when the data stored in the memory cell corresponds to a logical “0”, the data on the complimentary bit line for that cell will be a logical “1” and vice versa. Sense amplifier circuits may be coupled between complimentary bitlines to improve access to data stored in the memory cell. A sense amplifier amplifies a signal corresponding to the difference between two voltage levels. The output of a sense amplifier provides an early indication of whether the logic level of a given memory cell is going to change or remain unchanged.
As integrated circuit feature sizes continue to get smaller, distances between adjacent bitlines continue to decrease as well. Accordingly, there is an increasing possibility that adjacent device features, such as bitlines, may be short circuited to each other. In other words, adjacent bitlines may be unintentionally connected to each other during manufacture. If a short circuit develops between adjacent bitlines, the DRAM device may produce erroneous data when installed in an electronic device such as a computer system or the like. The electronic device in which the defective DRAM is installed may experience performance problems or may not function at all.